1. Technical Field
The present disclosure relates to a memory system, and more particularly, to a memory system including a multi-level cell (MLC) flash memory.
2. Discussion of the Related Art
Recently, the use of non-volatile memory in devices has increased. For example, MP3 players, digital cameras, mobile phones, camcorders, flash cards, and solid state disks use non-volatile memory as a storage device.
Similarly, there is a need for non-volatile memory with increased storage capacity. One method for increasing storage capacity is to use a multi-level cell (MLC) that stores a plurality of bits in one memory cell.
FIG. 1 is a block diagram of a conventional memory system. Referring to FIG. 1, a conventional memory system 100 includes a host 110, a memory controller 120, and a flash memory 130.
The memory controller 120 includes a buffer memory 121. The flash memory 130 includes a cell array 131 and a page buffer 132. Although not illustrated in FIG. 1, the flash memory 130 also includes a decoder, a data buffer, and a control unit.
The memory controller 120 receives data and a write command from the host 110, and the memory controller 120 controls the flash memory 130 to write the data in the cell array 131. Additionally, the memory controller 120 controls the flash memory 130 to read the data stored in the cell array 131 according to a read command inputted from the host 110.
The buffer memory 121 temporarily stores the data used for the flash memory 130 or the data read from the flash memory 130. The buffer memory 121 transmits the data that are temporarily stored by the control of the memory controller 120 into the host 110 or the flash memory 130.
The cell array 131 of the flash memory 130 includes a plurality of memory cells. The memory cells are non-volatile and thus retain their data when no power is applied. The page buffer 132 is a buffer for storing the data that is used for a selected page of the cell array or the data read from the selected page.
Each memory cell of the flash memory 130 is divided into a single level cell (SLC) and an MLC according to the number of data bits that can be stored. The SLC stores a single data bit and the MLC stores multi-bit data.
The SLC stores one bit in one memory cell. The SLC has two states according to the threshold voltage distribution. The memory cell stores either data 1 or data 0 after programming. Here, a memory cell storing the data 1 is in an erase state, and a memory cell storing the data 0 is in a program state. The cell in the erase state may be called an on cell and the cell in the program state may be called an off cell.
The flash memory 130 performs a program operation a page at a time. The memory controller 120 uses the buffer memory 121 therein to transmit the data into the flash memory 130 a page at a time during a program operation.
The page buffer 132 temporarily stores the data loaded from the buffer memory 121, and simultaneously programs the loaded data into a selected page. After completing a program, a program verify operation is performed to verify whether the data has been correctly programmed.
After the program verify operation, when program fail occurs, a program voltage increases and a program operation and a program verify operation are performed again. After programming the data in one page is completed using this method, the next data is received to perform a program operation.
The MLC stores multi-bit data in one memory cell. FIGS. 2 and 3 are views illustrating a process of programming a least significant bit (LSB) and a most significant bit (MSB), e.g., 2 bits, in one memory cell.
Referring to FIG. 2, the memory cell is programmed to have one state selected from the group consisting of four states 11, 01, 10, and 00 according to the threshold voltage distribution. A process of programming the LSB is identical to that of the SLC. The memory cell having a state 11 is programmed to have a dotted line state A depending upon the LSB data.
Next, the memory controller 120 transmits data of one page in the buffer memory 121 into the flash memory 130 for programming. Referring to FIG. 2, the memory cell having a dotted line state A is programmed according to program 1 to have a state 00, or programmed according to program 2 to have a state 10 depending upon the MSB. The memory cell having a state 11 maintains a state 11 or is programmed according to program 3 to have a state 01 depending upon the MSB.
Referring to FIG. 3, the memory cell is programmed to have one of four states 11, 01, 10, and 00 according to the distribution of the threshold voltage. First, the memory cell having a state 11 maintains a state 11 or is programmed according to program 1 to have a state 10 depending upon the LSB. Next the MSB is programmed. The memory cell having a state 10 maintains a state 10 or is programmed according to program 2 to have a state 00 depending upon the MSB. Moreover, the memory cell having a state 11 maintains a state 11 or is programmed according to program 3 to have a state 01 depending upon the MSB.
Referring to FIG. 1 again, the memory system 100 programs the multi-bit data into the cell array 131 of the flash memory 130 by using the same method. The LSB is programmed first and then the MSB is programmed on the memory cell where the LSB is programmed.
The conventional memory system 100 allocates two logical pages in one physical page. Here, the physical page is a group of memory cells connected to one word line. When 2 bit data is stored in the one memory cell, the flash memory 130 reads or programs the LSB and MSB, respectively. One physical page has two logical pages. The pages logically existing in one physical page are called logical pages.
After the LSB is programmed in one physical page, the MSB is programmed on the same physical page. In programming the LSB, a program speed is relatively fast, but in programming the MSB, a program speed is relatively slow.
When more than two logical pages are allocated into one physical page and thus there is one or more logical pages between the LSB logical page and the MSB logical page, the program speed becomes slower as the logical pages being programmed are closer to the MSB logical page. As the logical pages being programmed approach the MSB, the possibility of data error occurrence increases. Accordingly, the LSB has a relatively high reliability but the MSB has a relatively low reliability. For this reason, the reliability of logical pages allocated in one physical page varies according to the LSB and MSB.
To enhance data reliability, error correction code (ECC) or a channel coding technique can be used. However, when a plurality of logical pages are allocated into one physical page, data error possibility varies according to each of the logical pages. Therefore, there is a limit in applying the ECC or the channel coding technique.